1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and particularly to a semiconductor device having an element separation structure for obtaining good element characteristics and a manufacturing method of the semiconductor device for efficiently forming the element separation structure.
2. Description of the Background Art
Due to development of integration of semiconductor devices in recent years, improvements of formation processes of element separation structures have been strongly desired in order to obtain good element characteristics.
The element separation structure of the semiconductor device and the manufacturing method in the prior art will be described below with reference to FIGS. 1A-1D. These figures sequentially illustrate manufacturing processes of a semiconductor device in which transistors having large MOS (Metal Oxide Semiconductor) type LDD (Lightly Doped Drain) structures are formed in active regions in which element separation is effected by field shield parts.
In this prior art, a SiO.sub.2 film 2 of about 200 .ANG. in thickness is initially formed, e.g., by a thermal oxidation method on an entire area of a p-type semiconductor substrate 1 and a polysilicon layer 3 of about 2000 .ANG. in thickness is then formed thereon, e.g., by a vacuum CVD method. A SiO.sub.2 film 4 of about 2000 .ANG. in thickness is further deposited on an entire area of the polysilicon layer 3, e.g., by a CVD method (FIG. 1A).
Then, photolithography and etching are utilized to sequentially and selectively etch the SiO.sub.2 film 4, the polysilicon layer 3 and the SiO.sub.2 film 2 to form a field shield part 5. Thereafter, a SiO.sub.2 film of about 2000 .ANG. in thickness is deposited on an entire surface of the semiconductor substrate 1 by the CVD method or the like, and then a sidewall spacer 6 is formed on the sidewall of the field shield part 5 by anisotropic etching. Simultaneously, the surface of the semiconductor substrate 1 except for an area provided with the field shield part 5 is exposed (FIG. 1B).
Then, a SiO.sub.2 film 7 of about 200 .ANG. in thickness, a polysilicon layer 8 of about 2000 .ANG. in thickness and a SiO.sub.2 film 9 of about 2000 .ANG. in thickness are sequentially formed on the entire surface of the semiconductor substrate 1. The photolithography and etching are then used to sequentially etch the SiO.sub.2 film 9, the polysilicon layer 8 and the SiO.sub.2 film 7 to form a gate part 10. Then, an n-type impurity ion such as phosphorus or arsenic is irradiated to the entire area of the semiconductor substrate 1, whereby low density n-type diffusion layers 11 are formed, using the gate part 10 as a mask (FIG. 1C).
Then, a SiO.sub.2 film of about 2000 .ANG. in thickness is deposited on the entire surface of the semiconductor substrate 1, and the anisotropic etching is effected to form sidewall spacers 12 on sidewalls of the gate part 10. An n-type impurity ion such as phosphorus or arsenic is then irradiated to the entire area of the semiconductor substrate 1 to form high density n-type diffusion layers 13, using the gate part 10 and the sidewall spacers 12 as the mask (FIG. 1D).
The low density n-type diffusion layers 11 and the high density n-type diffusion layers 13 which are formed in the above processes form source/drain regions, whereby the field effect transistor of the MOS type LDD structure is formed.
However, there have been following problems in the semiconductor device and the manufacturing method thereof in the prior art stated above.
First, since there is a stepped portion or difference in level between the field shield part 5 and the surface of the semiconductor substrate in the active region, a so-called defocus may be caused in the process for forming the gate part 10. This defocus is caused by variation of a thickness of a resist film 16, which serves as a mask for forming the gate part 10 by the etching. More specifically, a portion of the resist film 16 covering an area for the gate part 10 has a thickness larger than that of the portion thereof covering the field shield part 5, so that the resist film 16 is left in a configuration indicated by dashed line in FIG. 2A in the photolithography processing. Consequently, the gate part 10 actually formed has a width b larger than a size a determined as a design value of the width of the gate part 10 by the patterning on the surface of the resist film 16.
A phenomenon of such defocus, a resolution R, a focus margin DF and a number NA of openings in an optical system for the photolithography have a following relationship.
Assuming that an irradiation light used in the photolithography has a wave length of .lambda., a following relational expression can be established between the resolution R, focus margin DF and opening number NA, as is already known. EQU R=0.6.lambda./NA (1) EQU DF=1.39R.sup.2 /.lambda. (2)
FIG. 2B illustrates a graph in which the resolution R is given by the abscissa, the focus margin DF is given by the ordinate, and the variation of the opening number NA is plotted with respect to three values of .lambda., i.e., 248 nm (KrF laser), 365 nm (i ray) and 436 nm (g ray). As shogun in FIG. 2C, the resolution R is represented as a space between resist films 22a and 22b on a portion 21 to be etched in a unit of .mu.m. The opening number NA is one of quantities which represent the resolution and brightness of the optical system, and is defined by a product (n sin.theta.) of a refractive index n of a medium and sine of a degree .theta. of an angle which is formed by an object point 23 on an optical axis located in the medium having the refractive index n with respect to a radius of an entrance pupil 24. The focus margin DF defines an allowable maximum length L of a resist film 25 by which the defocus is not caused, in other words, the allowable maximum length L by which the upper width a of the resist film 25 shown in FIG. 2E can be substantially equal to the width b thereof on the surface of an object 26 to be etched, and the focus margin DF represents the value by which the width a is substantially equal to the width b in a range of L/2&lt;DF. Even if the thickness of the resist film 16 satisfies the above inequality in the upper portion (thickness L.sub.1) of the field shield part 5, said inequality is not satisfied in the upper portion (thickness L.sub.2) of the gate part 10 and thus the defocus is caused, due to the difference .DELTA.L of level shown in FIG. 2A. Further, if the difference of level .DELTA.L is larger than the double of DF, the defocus is inevitably caused on the gate part 10.
As described above, if the defocus is caused at the element formation pattern in the active region, such a phenomenon is caused that there is a difference between the size of the exposure pattern in the photolithography of the resist film and the size of the actually formed element, and thus the element characteristics intended in the design cannot be obtained.
The second problem caused by the difference of level .DELTA.L is that a disadvantageous phenomenon is caused by debris which remains on the sidewall of the field shield part 5 in the etching process for forming the gate part 10.
The phenomenon by the residual debris is described below with reference to FIGS. 3A-3C. If there is a difference of level .DELTA.L, the debris 27 which is primarily formed of polysilicon is deposited on a lower part of the sidewall of the field shield part 5, which may cause the disadvantageous phenomenon such as short-circuiting between the adjacent gate parts and/or between other conductive wiring layers, as shown in FIG. 3A and FIG. 3B which is a cross section taken along line A--A in FIG. 3A.
The cause of the deposition of the debris 27 can be explained as follows with reference to FIG. 3A and FIG. 3C which is a cross section taken along line B--B in FIG. 3B. In the etching process for forming the pate part 10, the SiO.sub.2 film 9 is initially etched. In this step, the steep slant or stepped portion at the vicinity of the field part 5 causes the deposition of the component(s) of the etching gas on the surface of the polysilicon layer 8, resulting in a deposition film 28. This deposition film 28 serves as a mask which prevents the progress of the etching at an area immediately below it, and thus when the gate part 10 is completed, the debris 27 primarily composed of the polysilicon sticks onto a lower portion of the sidewall of the field shield part 5.
The problems described above are caused in such a case that the active regions are separately insulated from each other by the field shield, and is also similarly caused in such a case that the element separation insulator layer is formed, for instance, by a LOCOS method.